The many components and peripheral devices of both desktop and portable personal computers (PCs) consume a great deal of power even when they are not active. For this reason, power management systems have been developed which cause each component or peripheral device of a computer to operate in the lowest power consumption mode with respect to present demands thereon. One basic type of power management system commonly implemented on personal computers, especially portables, monitors various peripheral devices for I/O activity. After a predetermined period of I/O inactivity has elapsed, the computer is "powered down", i.e., the system clock is halted and power is removed from the hard disk drive, the floppy disk drive, the liquid crystal display (LCD), and miscellaneous system circuitry, thereby effecting more efficient use of remaining battery power.
More recently, improvements in the basic power management system have been introduced which include options such as blanking the liquid crystal display (LCD) or monitor screen after a predetermined period of I/O inactivity or turning off the hard disk drive motor after the hard disk drive has not been accessed for a predetermined period of time. Furthermore, there may be provided more than one reduced power consumption mode. For example, there may be a "stand by" mode in which certain components, such as the LCD and the hard disk drive motor, are caused to enter a reduced power consumption mode but the processing speed of the central processing unit (CPU) is not affected. In a "sleep" mode, nearly all of the functions of the PC are slowed or halted, including the CPU. From the standpoint of power consumption, the sleep mode is substantially equivalent to turning the PC off, except that no data is lost.
One area of power management that is not currently addressed by available power management systems concerns dynamic random access memory (DRAM) subsystems. DRAMs are composed of an array of memory cells, each of which comprises a transistor network and an intrinsic capacitor. In operation, the transistors are used to charge or discharge the capacitor, depending on whether a "1" or a "0" is to be stored in the cell. It is well known that, in order to maintain the integrity of the data stored in the cells, the cells must be periodically refreshed. Such refreshing may be accomplished by reading each row of the DRAM array into sense amplifiers in the DRAM and then writing the data back into the row, referred to as a "row-only refresh". Refreshing the DRAM subsystem consumes a large amount of power. For example, a single Toshiba 1 MB.times. 4 DRAM requires an average refresh current of approximately 100 mA to refresh the entire DRAM. Most PCs require more than one such DRAM, as they must contain an amount of DRAM sufficient to accommodate the largest application program executable on the PC. In most instances, large portions of a DRAM subsystem do not contain valid data and therefore need not be refreshed.
Presently, there is no means for refreshing: only those portions of DRAM that contain valid data. For this reason, much battery power is wasted refreshing unused DRAM cells. Because of the large amount of power consumed by DRAM refresh, the total amount of DRAM which may optimally be included in a system is limited by power consumption, rather than architectural, concerns.
Therefore, what is needed is a memory controller for selectively refreshing only those portions of system DRAM that contain valid data.